Power- and Area-efficient Single Siso Architecture of Turbo Decoder

In this paper, we propose a powerand area-efficient architecture of Turbo decoder. In order to improve the nonfunctional performance metrics such as power consumption and area, we use the trade-off method between bit error rate (BER) performance and the two non-functional performance metrics. Our proposed architecture shows about 16.7% reduction in power consumption and about 22.5% reduction in area compared to the general architecture.